Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
In the past, FPGAs accommodated only configuration of the entire array. Accordingly, with each change in a design or the addition of a design, a full configuration bitstream had to be generated for reconfiguring the entire FPGA. Newer FPGA architectures have been developed, however, which accommodate a partial reconfiguration of the array. For example, partial reconfiguration is supported by Virtex® and Virtex-II® series FPGAs, commercially available from Xilinx, Inc. With partial reconfiguration, new configuration data is loaded to configure a specific area of an FPGA, while the rest of the FPGA remains operational and unaffected by the reprogramming.
Partial reconfiguration may be used to dynamically configure an FPGA with specific circuits or “modules”. For example, modules may be inserted or removed within an FPGA during operation without affecting other portions of circuitry operating within the FPGA. To enable dynamic module configuration, the input/output interface to a module is designed such that the module can be isolated from other circuitry to which the module is connected when the module is being reconfigured. Heretofore, tri-state buffers were used at the module interface to electrically isolate a module undergoing removal, an initial or subsequent programming of programmable logic, or non-use from one or more other modules. This allowed circuitry within the FPGA to continue to operate, while taking a module undergoing configuration off-line. Routing signals through tri-state buffers, however, adversely affects timing within the FPGA.
Therefore, there exists a need in the art for dynamically connecting modules within a programmable logic device without tri-stating buffers to do so.